Sr Principal Design Engineer
Sr Principal Design Engineer
CADENCE- Posted a month ago
- Be among the first 10 applicants
Job Description
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
12-14 yrs of work experiences in VLSI domain with Master's/bachelor's degree in engineering Strong expertise in Verilog, HVL(SV, Specman e) with UVM/OVM/eRM methodology Expertise in assertions development/closure, constraint randomization, functional and code coverages, formal verification Expertise in test-bench development Strong RTL and GLS (w/ or w/o SDF) sim debug skills Should be able to manage project schedule and delivery independently
Should be good in Perl/Tcl scripting and automation
We're doing work that matters. Help us solve what others can't.
12-14 yrs of work experiences in VLSI domain with Master's/bachelor's degree in engineering Strong expertise in Verilog, HVL(SV, Specman e) with UVM/OVM/eRM methodology Expertise in assertions development/closure, constraint randomization, functional and code coverages, formal verification Expertise in test-bench development Strong RTL and GLS (w/ or w/o SDF) sim debug skills Should be able to manage project schedule and delivery independently
Should be good in Perl/Tcl scripting and automation
We're doing work that matters. Help us solve what others can't.
More Info
Key Skills
SV
assertions development
functional and code coverages
SDF sim debug
eRM methodology
test-bench development
closure constraint randomization
About Company
Skills:
Debugging, Test architecture definition, Scan Insertion, Timing constraints for test mode timing closure, Scan and ATPG for different fault models, LEC checks, Zero delay and timing simulations, RTL changes for DFT, Post silicon bring up, DFT ownership, IEEE1687 iJTAG compliant ICL PDL for functional manufacturing tests, Boundary scan ACJTAG IEEE 1500 implementation and verification, Low power CLP checks