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Job ID: 148297443
Skills:
automation, Ovm, Tcl Scripting, Verilog, Perl, test-bench development, GLS, Uvm, RTL, SV, SDF sim debug, Specman, HVL, functional and code coverages, closure constraint randomization, assertions development, eRM methodology, formal verification
Skills:
automation, Ovm, Tcl Scripting, Verilog, Perl, Uvm, GLS, RTL, SV, SDF sim debug, Specman, test-bench development, HVL, functional and code coverages, closure constraint randomization, assertions development, eRM methodology, formal verification
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