routing, RTL-to-GDS flows, Rtl Design, floorplanning, Physical Verification methodologies, Cadence, LVS, Physical Design, EDA Tools, ERC, Timing Closure, DRC, Placement, Synopsys, Siemens tools, Clock Tree Synthesis

Python, Tcl, EDA Tools, PrimeClosure, floorplanning, CTS, Innovus, Aspen, Sta, ICC2, IO Timing ECO, Physical Design, Tempus, Postroute Optimization, Seahawk, Placement, Timing Closure, DRC closure, EMIR drop

redhawk , Synopsys ICC2, PNR and signoff tools, Cadence Innovus, Physical Verification, IR EM mitigation, PDN methodology, floorplanning, STA constraints, physical design implementation, primetime, Tempus, Voltus

synopsys tools , Scripting, Soc Architecture, Physical Design, design validation, Microarchitecture, Design Principles

power optimization , routing, Perl, Python, Tcl, physical design flows, floorplanning, digital VLSI concepts, IR-drop, Timing Analysis, Tempus, voltus, Cadence Innovus, LVS, EM analysis, Physical Verification, Rtl Design, EDA Tools, DRC, Placement

redhawk , Shell, Tcl, Verilog, PERL, Innovus, floorplan exploration and optimization, Starrcxt, place and route methodologies, physical implementation and analysis tools, Fusion Compiler, power integrity and reliability analysis, Calibre, VHDL, low power physical design flows and methodologies, timing and signal integrity analysis, metal-only ECO implementation, power grid planning and implementation, timing optimization and timing closure, placement and optimization, Clock Tree Synthesis

Python, Tcl, primetime, StarRC, ICC2, DSO.ai, Synopsys Fusion Compiler

Flows, Physical Design, verbal and presentation skills, Design Methodologies, debugging skills, sign-off tools