static timing analysis, industry-standard EDA tools for physical design and verification, Synthesis, RTL-to-GDS workflows, multi-power domain analysis, low-power design techniques, Place And Route, Clock Tree Synthesis

synopsys tools , Scripting, Soc Architecture, Physical Design, design validation, Microarchitecture, Design Principles

rc extraction , Ecos, Sta, Scan Insertion, Physical Verification, LVS, Cadence synthesis, RTL-GDSII, Timing Closure, Dft, Synthesis, PNR, DRC, Physical design flow, Cross talk, Verification Tools, IR-EM checks, formal verification, Place And Route, Timing Analysis

routing, physical design flows, digital VLSI concepts, Tempus, floor-planning, Cadence Innovus, Voltus, Timing Closure, EDA Tools, Placement, Logic Synthesis, Rtl Design