Physical Design Engineer
- Posted 2 months ago
- Be among the first 20 applicants
Job Description
Key Responsibilities
- Physical Implementation: Perform floorplanning, power planning, placement, Clock Tree Synthesis (CTS), and routing for complex, timing-critical blocks or full-chip top-level integration.
- Signoff Closure: Ensure timing (STA), power integrity, and physical verification (DRC/LVS/ERC/ESD) closure on advanced technology nodes (5nm, 4nm, 3nm).
- Collaboration: Coordinate with RTL design, STA, and verification teams
Requirements & Qualifications
- Experience: 3–5 years on ASIC physical design.
- Tools: Strong expertise in Cadence Innovus or Synopsys ICC/ICC2.
- Technical Knowledge: Deep understanding of Netlist to GDSII flow
- Education: B.E/B.Tech or M.E/M.Tech in Electronics/Electrical
More Info
Job Type:
Industry:
Function:
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Key Skills
Cadence Innovus
Synopsys ICC
Netlist to GDSII flow
About Company
Skills:
Tcl, Routing, Perl, Netlist2GDSII Implementation, Power Integrity Analysis, primetime, Floor Planning, Physical Verification, Cadence Tools, Calibre, CTS, Innovus, Sta, ICC2, Physical Design Methodologies, Tk, Placement, PT-PX, sub-micron technology
Skills:
Voltus, Backend Signoff flows, Cell EM, LVS, SigEM, Power Grid planning, pegasus, Cadence Tools, Innovus, PERC, EMIR, Tempus, Esd, Signal and Power bump planning, DRC
Skills:
power optimization , routing, Perl, Python, Tcl, physical design flows, floorplanning, digital VLSI concepts, IR-drop, Timing Analysis, Tempus, voltus, Cadence Innovus, LVS, EM analysis, Physical Verification, Rtl Design, EDA Tools, DRC, Placement
Skills:
Cursor, Python, Tcl, Synthesis, standard place-and-route flows, Codex, Cadence Innovus, Claude, Place And Route, AI technologies, tool-specific scripting, RTL-to-GDSII flow, layout closure, timing convergence, AI concepts, design implementation, Physical Design, Synopsys ICC2, Clock Tree Synthesis
Skills:
Synthesis, primetime, RTL2GDS, Physical Design, EDA Tools, floorplanning, Synopsys Fusion Compiler, Cadence Innovus, Tempus