Physical Design Engineer

routing, Scripting Languages, Python, Perl, Tcl, power analysis, primetime, Fusion Compiler, Cadence Innovus, DFT insertion, manufacturing sign-off, Voltus, EDA Tools, low-power design, EM IR analysis, sign-off, advanced nodes, multi-clock domain handling, Synthesis, floorplanning, ASIC SoC physical design flows, Timing Analysis, Physical Verification, reliability checks, Signal Integrity, Timing Closure, Placement, Synopsys ICC2, Clock Tree Synthesis

cadence encounter , hardware engineering , redhawk , Shell, Python, Tcl, PPA quantification, EM IR signoff, flow development, Physical Verification, physical integration, RTL2GDS flow, Physical Design, CTS Routing, collateral generation, Scripting in Perl, Icc2 Innovus tools, ip development, Synopsys ICC2, formal verification, Timing Signoff

Tcl, Python, Perl, routing, Cadence Innovus, Timing Closure, Placement, CTS, floorplanning, Sta, ICC2

scripting in TCL, STA using Synopsys PrimeTime, Cadence Innovus, Synopsys ICC2, physical verification using Mentor Calibre

Routing, Perl, Tcl, Cadence Tools, Sta, CTS, sub-micron technology, ICC2, Power Integrity Analysis, Calibre, Innovus, primetime, Physical Verification, Timing Constraints, Placement, 28nm and lower technology nodes, Timing Closure, Tk, Floor Planning, Netlist2GDSII Implementation, Physical Design Methodologies, PT-PX