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Job Title: Physical Design Engineer (3+ Years Experience)
Job Summary:
We are looking for a talented Physical Design Engineer to work on block-level and full-chip implementation for advanced semiconductor designs. The role involves end-to-end physical design flow and achieving PPA (Power, Performance, Area) targets.
Key Responsibilities:
• Perform end-to-end physical design: floorplanning, placement, CTS, routing, and sign-off
• Optimize design for timing, power, and area (PPA)
• Handle timing closure and fix setup/hold violations
• Perform physical verification checks and ensure clean sign-off
• Work closely with RTL, STA, and DFT teams
• Support tape-out and ensure high-quality deliverables
• Contribute to flow improvements and automation
Required Skills:
• 3+ years of experience in Physical Design
• Hands-on experience with tools like Cadence Innovus / ICC2
• Strong knowledge of floorplanning, placement, CTS, routing
• Good understanding of timing closure and STA concepts
• Exposure to advanced technology nodes is a plus
• Scripting knowledge (TCL/Perl/Python) is preferred
Education:
• B.Tech / M.Tech in Electronics / Electrical / VLSI or related field
Location: Bengaluru
Experience: 3+ Years
Job ID: 146982885
Skills:
Perl Scripting, Sta, High Speed Cores, Circuit Level Comprehension, RTL to GDSII Implementation, Leakage Power, Signal Integrity, Multi-Vt Flow, IC design, Dfm, Power Supply Management, Deep Sub-Micron Design, Physical Design, Power Gating, High Frequency Design Convergence, PDN Methodology, PPA Targets, Timing Signoff
Skills:
Static Timing Analysis, Fusion Compiler, Physical Design Flow, floorplanning, ICC2, Innovus, primetime, Synthesis, Power Rail Grid Design, Mentor Graphics, Place And Route, Clock Tree Synthesis
Skills:
routing, Scripting Languages, Python, Perl, Tcl, power analysis, primetime, Fusion Compiler, Cadence Innovus, DFT insertion, manufacturing sign-off, Voltus, EDA Tools, low-power design, EM IR analysis, sign-off, advanced nodes, multi-clock domain handling, Synthesis, floorplanning, ASIC SoC physical design flows, Timing Analysis, Physical Verification, reliability checks, Signal Integrity, Timing Closure, Placement, Synopsys ICC2, Clock Tree Synthesis
Skills:
Scripting, PERL, Tcl, Sta, CTS, Full-chip Floor-planning, Timing Convergence, RTL2GDSII flow, ICC2, Tempus, primetime, Innovus, Physical Verification, Synthesis, Layout Closure, Physical Design, Timing Closure, High Frequency Design Methodologies, Place And Route
Skills:
Perl, Verilog, Python, Tcl, CTS, Post-Route Optimization, Synthesis, VHDL, Placement, CDNS, SNPS, P and R tools
We don’t charge any money for job offers
