routing, Scripting Languages, Python, Perl, Tcl, power analysis, primetime, Fusion Compiler, Cadence Innovus, DFT insertion, manufacturing sign-off, Voltus, EDA Tools, low-power design, EM IR analysis, sign-off, advanced nodes, multi-clock domain handling, Synthesis, floorplanning, ASIC SoC physical design flows, Timing Analysis, Physical Verification, reliability checks, Signal Integrity, Timing Closure, Placement, Synopsys ICC2, Clock Tree Synthesis

power optimization , Unix Shell, C, Linux, Tcl, Perl, Physical Design Flow, LVS, Block level PnR convergence, Cadence Innovus, Advanced STA Concepts, Physical Verification, Floor-planning, Synopsys ICC2, PDN, formal verification, PTSI Tempus, Place And Route, DRC, Timing Convergence, Timing Closure

Tcl, Python, Perl, routing, Cadence Innovus, Timing Closure, Placement, CTS, floorplanning, Sta, ICC2

scripting in TCL, STA using Synopsys PrimeTime, Cadence Innovus, Synopsys ICC2, physical verification using Mentor Calibre

Voltus, Backend Signoff flows, Cell EM, LVS, SigEM, Power Grid planning, pegasus, Cadence Tools, Innovus, PERC, EMIR, Tempus, Esd, Signal and Power bump planning, DRC

Shell, Perl, Python, Tcl, Pvs, Innovus, Conformal Low Power, Tempus, Cadence EDA tools

Routing, Perl, Tcl, Cadence Tools, Sta, CTS, sub-micron technology, ICC2, Power Integrity Analysis, Calibre, Innovus, primetime, Physical Verification, Timing Constraints, Placement, 28nm and lower technology nodes, Timing Closure, Tk, Floor Planning, Netlist2GDSII Implementation, Physical Design Methodologies, PT-PX