cadence encounter , Shell, Unix, Linux, Flow automation, Python Script, SDC STA and Equivalence checking, Tapeout sign-off experience, 10nm 7nm 5nm process nodes, Synopsys ICC2 tool set, Physical Design, PnR tools like ICC2 Innovus, Skill

Scripting, Perl, Tcl, Calibre, Innovus, Assura, Cv, ICC2, Cadence, EDA Tools, Verification Tools

Power Planning, Routing optimization, floorplanning, Placement, Debugging setup hold violations, Physical Verification, Physical Design ASIC implementation, Cadence Innovus

redhawk , Tcl, Perl, Python, SDC, Foundry PDKs, Implementation tool suite, EDA Tools, Power gating, Cadence, primetime, Tempus, Synopsys ICC2, CPF, Timing Analysis, TSMC, Physical Design, Synopsys, UPF, Cadence Innovus, Sta, Multi-voltage domains, Voltus, Signoff tools, Samsung, Low-power design techniques

Tcl, Routing, Perl, Netlist2GDSII Implementation, Power Integrity Analysis, primetime, Floor Planning, Physical Verification, Cadence Tools, Calibre, CTS, Innovus, Sta, ICC2, Physical Design Methodologies, Tk, Placement, PT-PX, sub-micron technology

Voltus, Backend Signoff flows, Cell EM, LVS, SigEM, Power Grid planning, pegasus, Cadence Tools, Innovus, PERC, EMIR, Tempus, Esd, Signal and Power bump planning, DRC

congestion management , Perl, Python, Tcl, physical implementation, SoC-level floorplanning, primetime, clock tree architecture, clock gating, Cadence Innovus, power-aware physical implementation, skew management, clock domain partitioning, clocking methodologies, Timing Closure, low-power design techniques, Synopsys ICC2