Tcl, Routing, Perl, Netlist2GDSII Implementation, Power Integrity Analysis, primetime, Floor Planning, Physical Verification, Cadence Tools, Calibre, CTS, Innovus, Sta, ICC2, Physical Design Methodologies, Tk, Placement, PT-PX, sub-micron technology

Voltus, Backend Signoff flows, Cell EM, LVS, SigEM, Power Grid planning, pegasus, Cadence Tools, Innovus, PERC, EMIR, Tempus, Esd, Signal and Power bump planning, DRC

power optimization , routing, Perl, Python, Tcl, physical design flows, floorplanning, digital VLSI concepts, IR-drop, Timing Analysis, Tempus, voltus, Cadence Innovus, LVS, EM analysis, Physical Verification, Rtl Design, EDA Tools, DRC, Placement

Cursor, Python, Tcl, Synthesis, standard place-and-route flows, Codex, Cadence Innovus, Claude, Place And Route, AI technologies, tool-specific scripting, RTL-to-GDSII flow, layout closure, timing convergence, AI concepts, design implementation, Physical Design, Synopsys ICC2, Clock Tree Synthesis

Synthesis, primetime, RTL2GDS, Physical Design, EDA Tools, floorplanning, Synopsys Fusion Compiler, Cadence Innovus, Tempus

automation, Python, Tcl, place-and-route, Cadence Innovus, Timing Analysis, Physical Verification