Physical Design Engineer
Physical Design Engineer
adroitec systems pvt ltd- Posted an hour ago
- Be among the first 10 applicants
Job Description
WE ARE HIRING | PHYSICAL DESIGN (PD) ENGINEERS
Company: Adroitec Systems Pvt. Ltd.
Experience: 2–10 Years
Location: Bengaluru / Hyderabad
Notice Period: Immediate to 30 Days Preferred
Job Description – Physical Design Engineer
We are looking for skilled Physical Design Engineers with hands-on experience in RTL-to-GDSII implementation and physical design flow.
Key Responsibilities:
- Experience in Physical Design implementation from RTL to GDSII.
- Hands-on experience in Floorplanning, Placement, CTS, Routing, and Timing Closure.
- Perform timing analysis, optimization, and congestion analysis.
- Work on setup/hold timing violations and timing closure.
- Experience with Physical Verification, including DRC and LVS.
- Knowledge of IR Drop, EM analysis, and signal integrity is an advantage.
- Work on power, performance, and area (PPA) optimization.
- Strong understanding of physical design fundamentals and EDA tools.
Required Skills:
- Hands-on experience with industry-standard tools such as Synopsys ICC2, Fusion Compiler, and
More Info
Job Type:
Industry:
Function:
Employment Type:
Key Skills
CTS
Power performance and area PPA optimization
Fusion Compiler
EM analysis
RTL-to-GDSII implementation
DRC
Physical design flow
Congestion analysis
Synopsys ICC2
About Company
Skills:
PERL, Python, Tcl, Sta, CTS, Full-chip Floor-planning, Timing Convergence, RTL2GDSII flow, ICC2, Tempus, Ir, primetime, Innovus, Synthesis, Physical Verification, Layout Closure, Physical Design, High Frequency Design Methodologies, Seahawk, Place And Route, ECO Timing Closure
Skills:
Physical Design Planning, Placement, Floor Planning
Skills:
Routing, Sta, CTS, PNR, Physical Design, floorplanning, Timing Closure, Placement, Sign-off
Skills:
C, Perl, Tcl, Clock Planning, Physical Verification, floorplanning, Timing Closure, Placement and Routing, Physical Design Implementation
Skills:
Design for Manufacturability, Physical Design, Timing Closure Methodologies, Placement and Routing, Design Rule Checks, Clock Tree Synthesis