PERL, Python, Tcl, Sta, CTS, Full-chip Floor-planning, Timing Convergence, RTL2GDSII flow, ICC2, Tempus, Ir, primetime, Innovus, Synthesis, Physical Verification, Layout Closure, Physical Design, High Frequency Design Methodologies, Seahawk, Place And Route, ECO Timing Closure

Physical Design Planning, Placement, Floor Planning

Routing, Sta, CTS, PNR, Physical Design, floorplanning, Timing Closure, Placement, Sign-off

C, Perl, Tcl, Clock Planning, Physical Verification, floorplanning, Timing Closure, Placement and Routing, Physical Design Implementation

Design for Manufacturability, Physical Design, Timing Closure Methodologies, Placement and Routing, Design Rule Checks, Clock Tree Synthesis

Verilog, System Verilog, python, Perl, Sta, Synthesis, Physical Verification, CTS, DFT tools, Extraction, Timing Analysis, Place And Route, Cadence, Synopsys

ML optimization tools (DSO.ai), CTS and routing, Timing-driven placement, PPA Optimization, floorplanning, Hierarchical physical design, RTL-to-GDS implementation flow, Synopsys Fusion Compiler, Pin assignment, Timing budgeting

power integrity , Timing Closure, Process node design rules, Physical Design methodologies, Cadence toolchain, Signal Integrity