Memory Layout Engineer

 MemoryLayout

• Role: Layout Design of SRAM/CAM/RF compiler memories in 5/3FF technology. 
• Responsibilities: Development of key building blocks of memory architecture such as Row Decoder, IO, Control. Skilled in pitched layout concepts, floor planning for Placement, Power and Global Routing. Compiler level integration, verification of Compiler/Custom memories. 
• Skills : Well experienced in using industry standard EDA tools like Cadence Virtuoso, Mentor Graphics Caliber etc. Good problem solving and logical reasoning skills. Good communication skills required 
• Experience : 3 to 7Years

The customer is looking for the following expertise:

1.     Understanding of memory architecture

2.      Experience in creating basic memorylayouts from scratch

3.      Knowledge of memory peripheral blocks, including control blocks, I/O blocks, and row drivers

The candidate should have over 3 years of experience with all of the above and more than 2 years of relevant industry experience overall. Additionally, they are seeking expertise in:

4.      Knowledge of compiler issues

5.      Understanding of reliability issues

6.      Simulation effects

7.      EMI (Electromagnetic Interference) considerations