Senior Memory layout Engineer
Senior Memory layout Engineer
smartsoc solutions pvt ltdEarly Applicant
- Posted 2 months ago
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Job Description
- Minimum 4+ years of experience with a Bachelor's degree in Engineering studies or Master's degree, strong layout knowledge.
- Proficiency in using Cadence tools (Virtuoso Layout, Layout XL, Cadence Schematic Capture, and verification tools - Calibre & Hercules).
- Strong layout knowledge in advanced submicron FinFET processes, including TSMC 5nm, 3nm, 2nm, A14 or Samsung lower FinFET nodes.
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Key Skills
About Company
Skills:
layout debugging, Parasitic Extraction, full-custom IC layout, Cadence Virtuoso, FinFET technology