matching , Routing, Hierarchical Layout, Parasitics, Memory Array Layout, floorplanning, NVM, Custom Layout, Sram, LVS, Memory Layout, Rom, Calibre, Physical Verification, Layout Optimization, Memory Compiler, PPA Optimization, Placement, ERC, DRC, Cadence Virtuoso, FinFET Technology

cadence schematic capture , Cadence Tools, Calibre, Hercules, Virtuoso Layout, Layout XL

physical closure, Synopsys, top-level memory integration, decoders, memory compiler IPs, bit-cell arrays, Sram, LVS, collaboration with circuit design, layout experience, sense amplifiers, power performance, yield manufacturability, verification PDK methodology teams, Cadence, optimize layouts for area, IR EM challenges, density verification, FinFET design rules, DFM guidelines, memory periphery, DRAM, DRC, layout and physical verification tools

Memory Management, Test Chip, Sram

cadence schematic capture , Cadence Tools, Memory layout design, AI automation in layout, CALIBRE, ElectroMigration, Hercules, SKILL Programming, Physical Verification, LVS, ERC, DRC, Script Programming, Antenna, Chip Integration, Floor-planning, Hierarchy layout