Search Jobs
Search by job, company or skills
Search by job, company or skills
This job is no longer accepting applications
4–6 years of experience in Memory or Custom Layout Design with strong expertise in memory architectures and layout optimization techniques.
Responsibilities:
Technical Skills:
Preferred Skills:
Job ID: 145567011
Skills:
routing, device placement, STA verification, yield optimization, custom memory design, CMOS device physics, circuit topology, layout automation, DFM compliance, floorplanning, layout-dependent effects, Layout Design, Cadence Virtuoso, IR reliability checks
Skills:
DRC LVS-clean layouts, industry-standard layout tools, advanced technology nodes, physical verification and sign-off flows, memory layout design
Skills:
PERL, Skill, Cadence LVS, Boundary conditions, LVS, memory architectures, ERC, Cadence Virtuoso layout editor, optimized layout design, DRC, Calibre physical verification flow, Finfet technology, layout design and verification tools
Skills:
fast simulation tools and waveform viewers, deep submicron technology challenges, NMDL and CCST libraries, writing SPICE decks stimulus and test vectors, FinFET technology, layout impact on speed capacitance power and area, generating libraries and performing QA sign-off, layout parasitic extraction, memory architectures and performance optimization, LVS DRC debugging skills and verification for lower technology nodes, memory leafcell layout design, EDA tools including Cadence SKILL scripting and automation for compiler flows and layout reuse
Skills:
Tcl, Python, Calibre DRC LVS, ICC, Cadence Virtuoso, QRC, Skill, StarRC
We don’t charge any money for job offers
