Senior Memory Layout Engineer
Location- Bengaluru
About the Role
We are seeking a highly skilled Senior Memory Layout Engineer with 5+ years of hands-on experience in custom memory design and layout. In this role, you will be responsible for developing high-density, low-power memory layouts at advanced technology nodes, ensuring manufacturability, reliability, and performance for next-generation SoCs.
Responsibilities
- Own end-to-end layout design of SRAM, Register Files, CAMs, and other custom memory blocks.
- Perform floorplanning, device placement, routing, and optimization for area, power, and performance.
- Ensure DRC/LVS/DFM compliance across multiple technology nodes (7nm, 5nm, and below).
- Collaborate with circuit design teams to translate schematics into robust physical layouts.
- Conduct parasitic extraction (PEX) and work closely with STA/verification teams for timing closure.
- Drive layout automation using scripting (SKILL, Tcl, Python) to improve productivity and consistency.
- Perform layout verification including EM/IR, reliability checks, and yield optimization.
- Interface with foundries and EDA vendors to adopt advanced methodologies and process improvements.
Basic Qualifications
- Bachelor's or Master's degree in Electrical Engineering, VLSI, or related field.
- 5+ years of experience in custom memory layout design.
- Strong expertise in Cadence Virtuoso and industry-standard layout tools.
- Solid understanding of CMOS device physics, circuit topology, and layout-dependent effects.
- Proven track record of delivering high-density memory layouts at advanced nodes.
- Familiarity with PEX, STA, and sign-off flows.
Preferred Qualifications
- Experience with multi-port SRAMs, low-power memories, and high-speed cache designs.
- Knowledge of FinFET layout techniques and advanced lithography constraints.
- Exposure to EDA automation and flow development for custom layout.
- Strong problem-solving skills and ability to work in fast-paced, cross-functional teams.
Why Join Us
- Work on cutting-edge memory IP powering next-generation silicon.
- Collaborate with world-class engineers in a highly innovative environment.
- Opportunity to own critical design blocks and influence product success.
- Competitive compensation, benefits, and career growth opportunities.
