routing, device placement, STA verification, yield optimization, custom memory design, CMOS device physics, circuit topology, layout automation, DFM compliance, floorplanning, layout-dependent effects, Layout Design, Cadence Virtuoso, IR reliability checks

DRC LVS-clean layouts, industry-standard layout tools, advanced technology nodes, physical verification and sign-off flows, memory layout design

PERL, Skill, Cadence LVS, Boundary conditions, LVS, memory architectures, ERC, Cadence Virtuoso layout editor, optimized layout design, DRC, Calibre physical verification flow, Finfet technology, layout design and verification tools

fast simulation tools and waveform viewers, deep submicron technology challenges, NMDL and CCST libraries, writing SPICE decks stimulus and test vectors, FinFET technology, layout impact on speed capacitance power and area, generating libraries and performing QA sign-off, layout parasitic extraction, memory architectures and performance optimization, LVS DRC debugging skills and verification for lower technology nodes, memory leafcell layout design, EDA tools including Cadence SKILL scripting and automation for compiler flows and layout reuse

Tcl, Python, Calibre DRC LVS, ICC, Cadence Virtuoso, QRC, Skill, StarRC

Perl, Tcl, Full-custom memory layout development, EDA Tools, ERC, EMIR analysis, DRC, LVS, Cadence Virtuoso

Perl, Tcl, EDA Tools, Skill, Cadence Virtuoso

shielding , power optimization , Memory Layout design, Statistical analysis of circuits, SRAM layouts, LVS, Custom Mixed-signal layouts, Dfm, EMIR, track planning, Basic concepts of matching, DRC, fabrication steps and flow, Reliability Analysis, analog mixed-signal design concepts, Circuit Design, Layout Design