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Memory Layout Engineer

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  • Posted 11 hours ago
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Job Description

Job Title: Memory Layout Engineer

Location: Bangalore

Job Type: Full-Time

Experience: 4-10 Years

Educational Qualification:

  • Bachelor's degree in Electrical or Electronics Engineering or equivalent Key Responsibilities
  • Design and development of critical memory layouts and provide integration support
  • Perform layout verification including LVS, DRC, EM checks, quality checks, and documentation
  • Deliver block-level and top-level layouts on time with acceptable quality standards
  • Plan, estimate area/time, schedule, delegate, and execute tasks to meet project milestones
  • Collaborate with cross-functional teams across multiple projects
  • Manage and resolve technical roadblocks and escalations to ensure timely delivery
  • Provide alternative technical solutions to clients where required
  • Build team capability to maintain operational excellence and customer service levels
  • Communicate effectively with engineering teams across different geographical locations

Required Skills & Experience:

  • Industry experience in memory leafcell layout design
  • Strong understanding of memory architectures and performance optimization
  • Strong knowledge of FinFET technology
  • Hands-on experience in memory domain including characterization, design, and validation
  • Proficiency in writing SPICE decks, stimulus, and test vectors
  • Experience with fast simulation tools and waveform viewers
  • Knowledge of layout parasitic extraction and deep submicron technology challenges
  • Strong LVS/DRC debugging skills and verification for lower technology nodes
  • Familiarity with EDA tools including Cadence SKILL scripting and automation for compiler flows and layout reuse
  • Familiarity with NMDL and CCST libraries
  • Experience in generating libraries and performing QA sign-off
  • Understanding of layout impact on speed, capacitance, power, and area
  • Ability to understand design constraints and implement high-quality layouts
  • Good problem-solving, critical thinking, and interpersonal skills

Note:

1. Applications will only be accepted through the ATS link provided above. Profiles shared through other means will not be considered.

2. We do not charge any fee from candidates at any stage. If anyone approaches you for money in exchange for this opportunity, treat it as fraud and report it to us immediately.

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Job ID: 147236611

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fast simulation tools and waveform viewersdeep submicron technology challengesNMDL and CCST librarieswriting SPICE decks stimulus and test vectorsFinFET technologylayout impact on speed capacitance power and areagenerating libraries and performing QA sign-offlayout parasitic extractionmemory architectures and performance optimizationLVS DRC debugging skills and verification for lower technology nodesmemory leafcell layout designEDA tools including Cadence SKILL scripting and automation for compiler flows and layout reuse