Perl, Shell scripting, DFT verification, Synopsys Tetramax DFTMAX, VCS simulation tool, IEEE1500, Scan memory BIST, JTAG 1149.x, Verilog RTL design, Design for Test methodologies, Mentor testkompress

scan compression, DFT architecture, ATPG, Scan Insertion, MBIST, Cadence DFT tools, test coverage analysis

boundary scan , bist , Jtag, Debugging, physical design constraints, Sta, verification flows, ATE test pattern generation, compression techniques, MBIST, Analytical Skills, TetraMax, Synopsys DFT Compiler, DFT tools, Tessent, silicon bring-up, Scan ATPG, LBIST, RTL design synthesis

DFT architecture, occ, compression at core level, coverage analysis, no-timing simulations, Memory-BIST, ATPG pattern generation, SSN architecture, Scan Insertion, timing simulations, clock architecture