Job Description: Design Verification Lead
Role: Design Verification Lead
Experience: 8+ years
Employment Type: Full-time
Role Overview
We are looking for an experienced Design Verification (DV) Lead to lead verification activities for complex ASIC/SoC designs. The ideal candidate will be responsible for defining verification strategies, leading teams, and ensuring high-quality delivery across projects.
Key Responsibilities
- Lead end-to-end functional verification for ASIC/SoC designs
- Define verification plans, methodologies, and coverage goals
- Architect and develop reusable, scalable verification environments
- Lead and mentor a team of verification engineers
- Drive testbench development using SystemVerilog, UVM
- Own functional, code, and assertion coverage closure
- Collaborate closely with design, DFT, and validation teams
- Review specifications, identify corner cases, and ensure robust verification
- Debug complex issues and drive resolution across teams
- Ensure adherence to schedules, quality, and best practices
Required Skills & Experience
- 8+ years of hands-on experience in Design Verification
- Strong expertise in SystemVerilog and UVM methodology
- Solid understanding of ASIC/SoC architecture
- Experience in building verification environments from scratch
- Proficiency in functional coverage, assertions (SVA), and scoreboards
- Strong debugging skills at block and SoC level
- Experience with industry-standard simulators and tools
- Prior experience in leading or mentoring verification teams
Good to Have
- Experience with low-power verification (UPF)
- Exposure to formal verification or emulation
- Scripting knowledge (Python, Perl, or Shell)
- Experience working on high-speed interfaces (PCIe, USB, DDR, Ethernet, etc.)
Soft Skills
- Strong communication and stakeholder management skills
- Ability to drive technical discussions and reviews
- Ownership mindset with attention to quality and timelines
