Altera is seeking a highly Technical Senior Design Verification Engineer/Lead for the FPGA IP team. The focus of this role is to plan, build, and execute the verification of new and existing features of Altera's FPGA Interface IPs, resulting in no bugs in the final design. This role requires exceptional technical depth across advanced DV methodologies and tools, combined with strong expertise in interconnect/serial protocols like Ethernet and PCIe.
Responsibilities:
- Design, develop, and deliver a comprehensive verification strategy and methodology that scales seamlessly for generation of products.
- Design and implement advanced verification environments, tools, and test-plans enabling first-pass silicon success; develop sophisticated testbenches, checkers, VIPs, and complex behavioral models.
- Collaborate closely with architecture, design, and software teams from initial product definition and specification reviews through implementation, bring up, and productization phases; balance complexity and ensure timely, high-quality execution.
- Drive ownership of multiple critical blocks and verification components; take full responsibility for functional signoffs and achievement of performance and power metrics.
- Lead IP delivery to multiple customers while ensuring technical excellence; balance competing requirements, schedules, and resource across teams.
- Champion innovation across simulation, formal, and accelerated verification methodologies; develop and evaluate new ML-based flows.
- Mentor and develop verification engineers; establish verification best practices and drive organizational technical excellence.
Qualifications:
- B.Tech/M.Tech in Electronics Engineering or related field.
- 10+ years of relevant experience in design verification.
- Strong background in simulation-based verification methodologies including UVM, ABV, and co-simulation; proficiency in System Verilog HDL and industry-standard EDA tools.
- Advanced hands-on coding proficiency across System Verilog/UVM, software programming languages (C/C++/), Scripting (Shell/Python/TCL).
- Excellent communication and organizational skills with a proven track record of delivering on-time, high-quality silicon and establishing technical standards.
Preferred Qualifications:
- Demonstrated experience with formal verification techniques, emulation or FPGA based Verification.
- Experience in Ethernet and/or PCIe protocols.
- Knowledge of FPGA design flow.
Additional Locations:
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
