Layout Engineer
Layout Engineer
smartsoc solutions pvt ltd- Posted 4 hours ago
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Job Description
SmartSoC Solutions Pvt. Ltd. is looking for talented Memory Layout Engineers to join our semiconductor design team.
Location: Bangalore
Experience: 3-8 Years
Notice Period: Immediate to 30 Days preferred
Key Skills:
• Strong experience in Memory Layout / Custom Layout
• Hands-on experience with Cadence Virtuoso
• Good knowledge of DRC, LVS, ERC & EM/IR
• Experience in Full-Custom Layout
• Exposure to Memory IPs / SRAM / ROM / Analog Blocks
• Knowledge of advanced technology nodes is an added advantage
Interested candidates can share their updated resumes at [Confidential Information]
Qualification: B.E./B.Tech/M.E./M.Tech – ECE / VLSI / Electronics
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Key Skills
About Company
Skills:
Shell, PERL, Tcl, Skill, DRC, LVS, Memory Layout
Skills:
matching , Routing, Foundry-specific PDK environments, Circuit Design concepts, floorplanning, Layout Design for analog and mixed-signal blocks, Physical Verification flows, LVS, ERC, DRC, CAD EDA tools, Cadence Virtuoso, Parasitic optimization
Skills:
Debugging, Physical Verification Tools, PEX, FinFET, LVS, Layout Optimization, ERC, DRC, Post-layout Verification, Analog Custom Layout, High-performance Analog Mixed-Signal Blocks, Advanced Technology Nodes, Cadence Virtuoso
Skills:
caliber , Verification Tools, Layout Design, Cadence Virtuoso
Skills:
Automation SKILL coding, Full chip layout experience, Analog and mixed-signal layout techniques, Device Matching, Power Bus design, ESD LU protection techniques, LVS DRC ERC and antenna debug skills