Analog Layout Engineer - 5+ Years for Bangalore location

Company Description LeadIC Design Pvt Ltd is a VLSI engineering company focused on accelerating semiconductor innovation through full-stack chip design and development expertise. Founded in 2018, LeadIC has grown into a trusted partner for global semiconductor companies, supporting the complete lifecycle from custom, memory, and analog layout to digital design, verification, and physical implementation. With engineering teams across India and Canada, the company delivers high-quality design services tailored to product-driven, technology-focused organizations. LeadIC emphasizes strong execution ownership, scalable offshore development centers, and a quality-driven culture that operates as an extension of client teams. The company's flexible engagement models and long-term partnerships reflect its commitment to reliable delivery and technical excellence.
Role Description This full-time Analog Layout Engineer role is based on-site in Bengaluru South. The engineer will be responsible for creating, optimizing, and validating analog and mixed-signal layout designs, ensuring compliance with foundry rules, performance targets, and reliability requirements. Day-to-day tasks include collaborating with circuit design engineers, implementing layout for analog blocks, running physical verification (DRC/LVS), and resolving layout-related issues. The role also involves reviewing schematics, performing layout-versus-schematic checks, optimizing for area, matching, and parasitics, and contributing to layout guidelines and best practices. The engineer will work closely with cross-functional teams to support tape-out, debug design problems, and maintain thorough documentation of layout work.
Qualifications

• Strong expertise in Layout Design for analog and mixed-signal blocks, including floorplanning, matching, routing, and parasitic optimization.
• Solid understanding of Circuit Design concepts, especially Analog and Analog Circuits, and their impact on layout implementation.
• Hands-on experience with Physical Verification flows, including DRC, LVS, ERC, and familiarity with industry-standard EDA tools.
• 5+ years of relevant experience in analog layout engineering for semiconductor/VLSI projects, preferably with exposure to advanced process nodes.
• Proficiency with CAD/EDA tools such as Cadence Virtuoso or equivalent, and comfort working in foundry-specific PDK environments.
• Strong problem-solving skills, attention to detail, and ability to work independently while collaborating effectively within engineering teams.
• Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, or a closely related discipline.
• Experience with mixed-signal SoC environments, tape-out processes, and global customer interactions is an advantage.