Shell, PERL, Tcl, Skill, DRC, LVS, Memory Layout

matching , Routing, Foundry-specific PDK environments, Circuit Design concepts, floorplanning, Layout Design for analog and mixed-signal blocks, Physical Verification flows, LVS, ERC, DRC, CAD EDA tools, Cadence Virtuoso, Parasitic optimization

Debugging, Physical Verification Tools, PEX, FinFET, LVS, Layout Optimization, ERC, DRC, Post-layout Verification, Analog Custom Layout, High-performance Analog Mixed-Signal Blocks, Advanced Technology Nodes, Cadence Virtuoso

caliber , Verification Tools, Layout Design, Cadence Virtuoso

Automation SKILL coding, Full chip layout experience, Analog and mixed-signal layout techniques, Device Matching, Power Bus design, ESD LU protection techniques, LVS DRC ERC and antenna debug skills

Pvs, Python, Tcl, Methodology, FinFET nodes, Floorplan to Tape-out, Reliability Effects, Layout Techniques, Scripting in SKILL, Circuit Analysis, Verification, ESD Latch-Up, LDE Reliability, Assura, Calibre, Physical Verification, Collaboration, Project Cycles, Analog RF Layout, Power Routing, Cadence Virtuoso

Python, Tcl, QRC, StarRC, Skill, ICC, Cadence Virtuoso, Calibre DRC LVS