Senior Analog Layout Engineer
Senior Analog Layout Engineer
leadsoc technologies pvt ltd- Posted 19 hours ago
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Job Description
Senior Analog Layout Engineer
Location: Bengaluru
Experience: 5–10 Years
Role Overview
We are looking for a Senior Analog Layout Engineer with strong hands-on experience in custom/analog layout at advanced technology nodes, including FinFET.
Key Responsibilities
- Develop high-quality analog/custom layouts for complex IC designs.
- Work on advanced-node layouts across FinFET technologies such as 5nm, 7nm, 3nm and below.
- Execute floorplanning, placement, routing and layout optimization for analog/mixed-signal blocks.
- Strong understanding of matching, symmetry, common-centroid, interdigitation and shielding techniques.
- Optimize layouts for area, parasitics, performance, matching and reliability.
- Perform DRC, LVS, ERC and PEX and resolve physical verification issues.
- Work closely with Analog Design, Circuit Design, P&R and Verification teams.
- Analyze and minimize parasitic effects and coupling in advanced-node designs.
- Support post-layout simulation, design iterations and tape-out activities.
Required Skills
- 5–10 years of Analog/Custom Layout experience.
- Strong experience in advanced technology nodes and FinFET.
- Hands-on experience with Cadence Virtuoso and physical verification tools.
- Strong understanding of analog layout fundamentals and advanced matching techniques.
- Experience with DRC, LVS, ERC, PEX and post-layout verification.
- Exposure to low-voltage, high-speed and high-performance analog/mixed-signal blocks.
- Experience with 5nm/7nm/3nm or similar advanced nodes is highly preferred.
- Strong debugging and layout optimization skills.
More Info
Job Type:
Industry:
Function:
Employment Type:
Key Skills
Physical Verification Tools
PEX
FinFET
Layout Optimization
DRC
Post-layout Verification
Analog Custom Layout
High-performance Analog Mixed-Signal Blocks
Advanced Technology Nodes
About Company
Skills:
Synopsys IC Validator, 7nm FinFET technology, multi-patterning awareness, Cadence Virtuoso Layout Suite, Cadence Pegasus, high-speed analog and mixed-signal layout design, Calibre DRC LVS PEX, device matching, LVS, extracted netlists, Custom Compiler, ERC checks, DRC, parasitic optimization, reliability rules
Skills:
reliability driven layout practices, Calibre, analog mixed-signal IC layout, PEX, DRC, parasitic-aware layout, antenna rules, post-layout simulation correlation, LVS, Cadence Virtuoso
Skills:
FinFET GAA layout concepts, Cadence Virtuoso Custom Layout, Calibre PVS, advanced-node analog custom layout, PEX, parasitic optimization, physical verification flows, post-layout simulation correlation, matching shielding guard rings isolation
Skills:
Design Rule Checks (DRC), Layout-versus-Schematic (LVS), Analog Circuit Design, Post-silicon debug, Custom Layout, Floor Planning, Foundry-specific design guidelines, Analog Layout Design, Device matching, Parasitic-aware layout optimization
Skills:
caliber , Verification Tools, Layout Design, Cadence Virtuoso