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DFT Engineer
Experience - 5+years
Location- Bangalore/Hyderabad
Experience with Chip level DFT and Post Silicon debug / analysis
Understanding of DFT architectures like :
a. ATPG Pattern generation
b. ATPG coverage analysis
c. Pattern simulation ( both timing/no timing)
d. Pattern Retargeting
e. Understanding JTAG/IJTAG
f. MBIST and Logic BIST
Job ID: 149369797
Skills:
Vcs, ATE patterns, Scan Insertion, Tessent, JTAG protocols, ATPG, Gate level simulation, Post-silicon validation, P1687, TestMax, TetraMax
Skills:
DFT Design, MBIST, Scan Chains, Scan Compression, TAP, ATPG
Skills:
Vcs, Perl, Python, Tcl, Scan Insertion, Post-silicon validation, P1687, TetraMax, Gate level simulation debugging, ATE patterns, JTAG protocols, ATPG, Tessent tool sets, TestMax
Skills:
Vcs, Perl, Python, Tcl, Scan Insertion, Post-silicon validation, P1687, TetraMax, ATE patterns, Tessent, JTAG protocols, ATPG, Gate level simulation, TestMax
Skills:
Static Timing analysis, Boundary Scan inserting tap controller, generating TDL for ATE, DFT simulation with and without SDF, analysing and improving scan coverage, P1500, Synthesis and formal verification tools, RTL based and netlist-based insertion flows, Stuck-At and At-Speed Faults, Inserting Scan and generating ATPG vectors, characterization DC Characteristics, DFT tools from Mentor, MBIST insertion and simulation
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