Vcs, ATE patterns, Scan Insertion, Tessent, JTAG protocols, ATPG, Gate level simulation, Post-silicon validation, P1687, TestMax, TetraMax

DFT Design, MBIST, Scan Chains, Scan Compression, TAP, ATPG

Vcs, Perl, Python, Tcl, Scan Insertion, Post-silicon validation, P1687, TetraMax, Gate level simulation debugging, ATE patterns, JTAG protocols, ATPG, Tessent tool sets, TestMax

Vcs, Perl, Python, Tcl, Scan Insertion, Post-silicon validation, P1687, TetraMax, ATE patterns, Tessent, JTAG protocols, ATPG, Gate level simulation, TestMax

Static Timing analysis, Boundary Scan inserting tap controller, generating TDL for ATE, DFT simulation with and without SDF, analysing and improving scan coverage, P1500, Synthesis and formal verification tools, RTL based and netlist-based insertion flows, Stuck-At and At-Speed Faults, Inserting Scan and generating ATPG vectors, characterization DC Characteristics, DFT tools from Mentor, MBIST insertion and simulation

boundary scan , Scripting, Jtag, Perl, Tcl, Scan Insertion, Yield analysis, DFT methodologies, MBIST, Debugging silicon test issues, ATPG, Programming using Python