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Exp: 3+ Years
Location: Bangalore, Chennai, Kochi & Pune
Skills and Experience Required
Hands on experience in Inserting Scan and generating ATPG vectors for
Stuck-At and At-Speed Faults. In-depth experience in analysing and improving scan coverage
Hands on experience in MBIST (insertion and simulation)
Experience in Boundary Scan, inserting tap controller and P1500
Experience in RTL based and netlist-based insertion flows
Experience in DFT simulation with and without SDF Experience in Synthesis and formal verification tools
Experience in characterization (DC Characteristics)
Experience in generating TDL for ATE and working closely with ATE team during bring-up phase
Good exposure to DFT tools from Mentor, Synopsys and Cadence
Good scripting know-how in Perl and TCL
Experience in Static Timing analysis preferred
Educational Qualification: BE/ME or BTech /MTech
Job ID: 149069347
Skills:
logic bist , Jtag, PERL, Shell script, Python, E-fuse, Pattern Retargeting, Post Silicon debug analysis, Pattern simulation, DFT architectures, Chip level DFT, ATPG Pattern generation, JTAG BSDL, scan chain insertion and verification, SDC constructs for DFT modes, Digital design concepts, pattern generation for Memories, stuck at IDDQ, MBIST, Scan Compression Techniques, JTAG IJTAG, ATPG coverage analysis, Transition faults, scan patterns and coverage statistics
Skills:
Perl, Python, Tcl, Scan insertion compression, Fault simulation coverage analysis, JTAG Boundary Scan, ATPG, DFT concepts and methodologies, MBIST, LBIST
Skills:
boundary scan , static timing analysis, Jtag, Verilog, System Verilog, Python, Tcl, gate-level simulations, DFT techniques, scan compression, UVM methodology, Scan Insertion, DFT methodologies, memory BIST, MBIST, VHDL, ATPG, Tk, RTL Coding, multi-vendor DFT tools
Skills:
ATE silicon debug, Verilog Hdl, MBIST insertion simulation and debug on RTL and gates netlist, Scan insertion with compression for Stuck-At and At-Speed test, Simulators and waveform debugging tools, Scan ATPG Stuck-At and At-Speed coverage analysis simulation and debug, Boundary Scan insertion simulation and verification
Skills:
Perl, Tcl Scripting, Scan Insertion, Gate level simulations, SCAN DRC Coverage debug, ATPG Pattern generation, Zero delay Timing Delay simulations, PD flow knowledge, Timing Formal verification, JTAG P1500 protocols
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