logic bist , Jtag, PERL, Shell script, Python, E-fuse, Pattern Retargeting, Post Silicon debug analysis, Pattern simulation, DFT architectures, Chip level DFT, ATPG Pattern generation, JTAG BSDL, scan chain insertion and verification, SDC constructs for DFT modes, Digital design concepts, pattern generation for Memories, stuck at IDDQ, MBIST, Scan Compression Techniques, JTAG IJTAG, ATPG coverage analysis, Transition faults, scan patterns and coverage statistics

Perl, Python, Tcl, Scan insertion compression, Fault simulation coverage analysis, JTAG Boundary Scan, ATPG, DFT concepts and methodologies, MBIST, LBIST

boundary scan , static timing analysis, Jtag, Verilog, System Verilog, Python, Tcl, gate-level simulations, DFT techniques, scan compression, UVM methodology, Scan Insertion, DFT methodologies, memory BIST, MBIST, VHDL, ATPG, Tk, RTL Coding, multi-vendor DFT tools

ATE silicon debug, Verilog Hdl, MBIST insertion simulation and debug on RTL and gates netlist, Scan insertion with compression for Stuck-At and At-Speed test, Simulators and waveform debugging tools, Scan ATPG Stuck-At and At-Speed coverage analysis simulation and debug, Boundary Scan insertion simulation and verification

Perl, Tcl Scripting, Scan Insertion, Gate level simulations, SCAN DRC Coverage debug, ATPG Pattern generation, Zero delay Timing Delay simulations, PD flow knowledge, Timing Formal verification, JTAG P1500 protocols

Jtag, static timing analysis, Scripting Languages, Hdl, memory test concepts, ECO handling, ASIC design flow, gate-level simulation, scan compression, IEEE 1149.1, Scan ATPG, DFX, Verification, Dft

memory test , boundary scan , Digital Logic Design, static timing analysis, Hdl, Jtag, DFX verification, HTOL, test clocking, security mechanisms, compression techniques, IDDQ, IEEE1149.1, Gates verification, Eco, ATPG, BIST architecture, silicon bring-up, Scan ATPG, ASIC Logic Design Flow, reliability tests