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Job ID: 147372359
Skills:
rtl verification , SoC-level DFT architecture implementation, LINT, Synthesis, ATPG, DFT timing, DFT Embedded Deterministic Test EDA tool Tessent, SoC DFT RTL implementation, MBIST, Low Power designs
Skills:
boundary scan , bist , DFT Engineering, Pattern Retargeting, Coverage analysis and improvement, Scan Chains, Xelium, Synopsys DFT Compiler, Scan Insertion, ATPG, DFT DRC Debugging and Resolution, Test Kompress
Skills:
Vcs, System Verilog, JTAG protocols, ATPG, Logic Equivalency checking, Gate level simulation debugging, Scan and BIST architectures
Skills:
Perl, Logic Design, Python, DFT Engineering, SV, Post Silicon Testing, Coverage metrics, Constrained random testing, Uvm, Profiling Tools, Architecture Verification
Skills:
Soc Architecture, tessent DFT, DFT architecture definition, HDLs, Genus, Scan, Cadence digital implementation tools, Tempus, MBIST, JTAG boundary scan, ATPG flow implementation
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