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One of our Client looking for a DFT Engineer with practical experience in scan-based testing and ATPG for ASIC/SoC designs.
What you'll work on
What we're looking for
Job ID: 146707597
Skills:
boundary scan , Digital Logic Design, Jtag, Perl, Verilog, Loopback, Python, Tcl, Timing Analysis, MBIST, DFT methodologies, Siemens Tessent, circuit fundamentals, compressed scan, IEEE 1500, IEEE 1687, ATPG coverage analysis, Cadence Modus, Genus, SDF-based simulations
Skills:
Perl, Shell scripting, DFT verification, Synopsys Tetramax DFTMAX, VCS simulation tool, IEEE1500, Scan memory BIST, JTAG 1149.x, Verilog RTL design, Mentor testkompress, Design for Test methodologies
Skills:
boundary scan , Static Timing analysis, SDF, ATPG vectors, Tap controller, MBIST insertion, DFT simulation, Netlist-based insertion flows, P1500, Formal verification tools
Skills:
Vcs, System Verilog, primetime, Logic Equivalency checking, TetraMax, JTAG protocols, Tessent, Gate level simulation, ATPG, EDA Tools, BIST architectures, TestMax
Skills:
Compressor-based scan chain insertion, Analog BIST implementation
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