Perl, Shell scripting, DFT verification, Synopsys Tetramax DFTMAX, VCS simulation tool, IEEE1500, Scan memory BIST, JTAG 1149.x, Verilog RTL design, Mentor testkompress, Design for Test methodologies

boundary scan , Digital Logic Design, Jtag, Perl, Verilog, Loopback, Python, Tcl, Timing Analysis, MBIST, DFT methodologies, Siemens Tessent, circuit fundamentals, compressed scan, IEEE 1500, IEEE 1687, ATPG coverage analysis, Cadence Modus, Genus, SDF-based simulations

boundary scan , Static Timing analysis, SDF, ATPG vectors, Tap controller, MBIST insertion, DFT simulation, Netlist-based insertion flows, P1500, Formal verification tools

Jtag, Test Strategy, Python, Tcl, compression boundary scan, scan architecture, DFT specifications, MBIST repair, STA debug, SDC, IO and clock constraints, ATPG, SSN methodology, DFT timing constraints, 1500 iJTAG, hierarchical DFT methodology

Vcs, System Verilog, primetime, Logic Equivalency checking, TetraMax, JTAG protocols, Tessent, Gate level simulation, ATPG, EDA Tools, BIST architectures, TestMax

Compressor-based scan chain insertion, Analog BIST implementation

Tcl Scripting, Perl, Dft, Gate level simulations, Zero delay Timing Delay simulations, PD flow knowledge, ATPG Pattern generation, Timing Formal verification, JTAG P1500 protocols, SCAN DRC

Jtag, Python, Perl, Uvm, SV, Memory BIST, ATPG, NVIDIA custom tools

Perl, Python, Tcl, Applied Machine Learning, generative AI solutions, statistical tools for data analysis, DFT VLSI concepts