Job Description
About the Role:
Tesla's Silicon Development Group is seeking a DFT Engineer
to drive Design-for-Test across the design-to-production lifecycle
for custom ASICs. In this role, you will own testability from design through silicon bring-up and high-volume manufacturing. You will advance state-of-the-art methodologies in test, debug, and safety to achieve high coverage, exceptional quality, and ultra-low DPPM—while optimizing test cost at scale.
Responsibilities:
Define and implement DFT features at RTL and gate levels using in-house flowsPartner with physical design teams to achieve timing and design closure with DFT constraintsExecute block-level scan insertion, ATPG, coverage analysis, and simulationsPerform full-chip pattern retargeting, validation, and sign-offDrive design improvements to enhance test coverage and diagnosabilityCollaborate with test and product engineering on pattern delivery, silicon bring-up, debug, and characterization
Requirements:
Strong understanding of DFT methodologies including compressed scan, MBIST, loopback, and boundary scan across digital logic, embedded memory, and IO/PHY domainsSolid knowledge of JTAG, IEEE 1500, and IEEE 1687; familiarity with BSDL, ICL, and PDL is a plusProven expertise in ATPG, coverage analysis, and both zero-delay and SDF-based simulationsExperience with industry-standard DFT tools such as Cadence Modus/Genus or Siemens TessentStrong foundation in Verilog, digital logic design, circuit fundamentals, and timing analysisProficiency in scripting (TCL, Python, or Perl)Experience with MBIST implementation, repair algorithms, and memory test strategies is a plusExposure to SerDes and mixed-signal DFT techniques (e.g., IOBIST, loopbacks) is a plusPost-silicon experience including pattern conversion, bring-up, debug, and characterization is a plusBachelor's or Master's degree in Electrical or Computer Engineering (or equivalent experience)
