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Skills and Experience Required
Hands on experience in Inserting Scan and generating ATPG vectors for
Stuck-At and At-Speed Faults. In-depth experience in analysing and improving scan coverage
Hands on experience in MBIST (insertion and simulation)
Experience in Boundary Scan, inserting tap controller and P1500
Experience in RTL based and netlist-based insertion flows
Experience in DFT simulation with and without SDF Experience in Synthesis and formal verification tools
Experience in characterization (DC Characteristics)
Experience in generating TDL for ATE and working closely with ATE team during bring-up phase
Good exposure to DFT tools from Mentor, Synopsys and Cadence
Good scripting know-how in Perl and TCL
Experience in Static Timing analysis preferred
Educational Qualification: BE/ME or BTech /MTech
Job ID: 147549427
Skills:
Perl, Shell scripting, DFT verification, Synopsys Tetramax DFTMAX, VCS simulation tool, IEEE1500, Scan memory BIST, JTAG 1149.x, Verilog RTL design, Mentor testkompress, Design for Test methodologies
Skills:
boundary scan , Digital Logic Design, Jtag, Perl, Verilog, Loopback, Python, Tcl, Timing Analysis, MBIST, DFT methodologies, Siemens Tessent, circuit fundamentals, compressed scan, IEEE 1500, IEEE 1687, ATPG coverage analysis, Cadence Modus, Genus, SDF-based simulations
Skills:
Jtag, Test Strategy, Python, Tcl, compression boundary scan, scan architecture, DFT specifications, MBIST repair, STA debug, SDC, IO and clock constraints, ATPG, SSN methodology, DFT timing constraints, 1500 iJTAG, hierarchical DFT methodology
Skills:
Tcl Scripting, Perl, Dft, Gate level simulations, Zero delay Timing Delay simulations, PD flow knowledge, ATPG Pattern generation, Timing Formal verification, JTAG P1500 protocols, SCAN DRC
Skills:
Jtag, static timing analysis, Scripting Languages, Hdl, memory test concepts, ECO handling, ASIC design flow, gate-level simulation, scan compression, IEEE 1149.1, Scan ATPG, DFX, Verification, Dft
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