Fpga, DDR, High Speed SERDES, Test Development, RTL Custom Logic design, MBIST, Mixed Signal IPs, Verification, ATE test, P R STA Integration, Pll, tool development methodology, Synthesis, DFT EDA tools, multi-processors SOC, characterization, SOC Scan

logic bist , Jtag, PERL, Shell script, Python, E-fuse, Pattern Retargeting, BSDL, Pattern simulation, Post Silicon debug analysis, DFT architectures, IDDQ, Chip level DFT, Fault Models, ATPG Pattern generation, scan chain insertion and verification, SDC constructs for DFT modes, Digital design concepts, pattern generation for Memories, MBIST, Scan Compression Techniques, JTAG IJTAG, ATPG coverage analysis, Transition faults, stuck at, scan patterns and coverage statistics

boundary scan , Vcs, Perl, Python, Tcl, Scan Insertion, Post-silicon validation, P1687, TetraMax, Gate level simulation debugging, ATE patterns, JTAG protocols, ATPG, Tessent tool sets, TestMax

Vcs, ATE patterns, Scan Insertion, Tessent, JTAG protocols, ATPG, Gate level simulation, Post-silicon validation, P1687, TestMax, TetraMax

DFT features, DFT signoff, IO BIST, test access mechanisms, ATPG, Scan Insertion, memory BIST, test coverage driven ATPG closure

Vcs, Perl, Python, Tcl, Scan Insertion, Post-silicon validation, P1687, TetraMax, Gate level simulation debugging, ATE patterns, JTAG protocols, ATPG, Tessent tool sets, TestMax