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Job Description :
Principal Accountabilities
Work with multi-functional teams to implement designs in test access mechanisms, IO BIST, memory BIST, scan insertion and ATPG, IP Tests.
* Develop methodologies to verify DFT features in complex IP's/Sub-systems/SOC's.
* Collaborate to drive test coverage driven ATPG closure and DFT signoff.
Exp : Minimum 4+ years
Job Complexity
Job complexity may vary among jobs within this job level and will align with one of the job complexities listed below:
(1) Incumbent has limited level of discretion to vary from established procedures, works under general supervision, and solves some straightforward problems. Incumbent generally has limited work experience involving basic concepts and procedures but requires formal training in theories/concepts in own function.
(2) Incumbent has high level of discretion to vary from established procedures, works under broad supervision, and solves some complex problems. Incumbent generally has substantial work experience involving complex concepts and procedures in theories/concepts in own function.
Job ID: 149172857
Skills:
logic bist , Jtag, PERL, Shell script, Python, E-fuse, Pattern Retargeting, BSDL, Pattern simulation, Post Silicon debug analysis, DFT architectures, IDDQ, Chip level DFT, Fault Models, ATPG Pattern generation, scan chain insertion and verification, SDC constructs for DFT modes, Digital design concepts, pattern generation for Memories, MBIST, Scan Compression Techniques, JTAG IJTAG, ATPG coverage analysis, Transition faults, stuck at, scan patterns and coverage statistics
Skills:
industry-standard DFT EDA tools, DFT flow, Scan Insertion, timing generating test cases, verification for complex ASIC SoC designs, DFT validation, VLSI ASIC design flows, debugging GLS
Skills:
boundary scan , Vcs, Perl, Python, Tcl, Scan Insertion, Post-silicon validation, P1687, TetraMax, Gate level simulation debugging, ATE patterns, JTAG protocols, ATPG, Tessent tool sets, TestMax
Skills:
Vcs, ATE patterns, Scan Insertion, Tessent, JTAG protocols, ATPG, Gate level simulation, Post-silicon validation, P1687, TestMax, TetraMax
Skills:
Vcs, Perl, Python, Tcl, Scan Insertion, Post-silicon validation, P1687, TetraMax, Gate level simulation debugging, ATE patterns, JTAG protocols, ATPG, Tessent tool sets, TestMax
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