DFT Engineer
DFT Engineer
ambit semiconductors private limited- Posted 2 hours ago
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Job Description
- Job Title: DFT Engineer
- Experience: 5–10 years
- Notice Period: 15 to 30 days
- Location: Bangalore
Role and Responsibilities:
- Person will be responsible for scan insertion, stuck_at & at-speed ATPG, scan simulations and post silicon debugging for hierarchical design.
- Skill Requirements: Person should have good hands-on experience in SCAN, ATPG , Scan pattern verification and also should have good understanding of scan constraints.
- Good to have: Knowledge of MBIST
More Info
Key Skills
About Company
Skills:
boundary scan , Debugging, Tessent tools, coverage analysis, clock analog observe PLL RO, DFT – Scan ATPG, thermal sensors, SSN EDT, JTAG networks, DFX DV for IP debug units, TDR verification, clock-stop features, scan pattern generation, test-case development, AFM fault models, scan pattern simulation, root-cause analysis
Skills:
boundary scan , Perforce, Jtag, Git, Perl, Tcl, Verilog Hdl, Synopsys SMS SHS flow, Scan DRC flows, Mentor, Cadence, Siemens Tessent, AT-Speed SCAN, Dft, ATE silicon debug, EDA Tools, IJTAG, Multimedia subsystems DFT, MBIST, Shell flow, IO BIST, ATPG, Stuck-AT, Synopsys
Skills:
perl, Vcs, Jtag, shell scripting, Awk, Design Compiler, Verdi, Fusion Compiler, BIRA, NCSim, MBIST, Tessent, ATPG, TetraMax Tool, BISR, Modelsim, Tester scan
Skills:
Synthesis, ASIC SOC design flow, Scan Insertion, digital design fundamentals, JTAG Boundary Scan, ATPG, Scan Compression, MBIST, STA concepts, DFT Verification
Skills:
test case generation , perl, Vcs, shell scripting, Awk, Design Compiler, Verdi, Fusion Compiler, BIRA, Tessent MBIST, TMBIST tool, NCSim, ATPG Coverage Improvement, Debugging Simulation Mismatches, MBIST Implementation, Tessent, Stuck-AT At-Speed Pattern Generation, Scan DRC fixing, TetraMax Tool, BISR, Modelsim, ATPG MBIST TestBench Validation, Scan Insertion