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DFT Engineer

DFT Engineer

Capgemini
12-14 Years
Not Disclosed
  • Posted 11 hours ago
  • Be among the first 10 applicants

Job Description

Location: Bangalore / Hyderabad / Chennai/Pune

Experience: 12 Years

Job Description

We are seeking a highly motivated DFT Engineer to join our ASIC/SOC Design team. The candidate will be responsible for implementing and verifying DFT features to improve testability and manufacturing quality of complex SOC/ASIC designs.

Key Responsibilities

  • Develop and implement DFT architecture for ASIC/SOC designs.
  • Insert and verify Scan, MBIST, LBIST, Boundary Scan (JTAG), and Compression logic.
  • Work on ATPG pattern generation and fault coverage analysis.
  • Perform DFT verification, simulation, and debugging.
  • Collaborate with Design, Verification, Physical Design, and Test teams.
  • Analyze test coverage and optimize DFT methodologies.
  • Support silicon bring-up, failure analysis, and yield improvement activities.

Mandatory Skills

  • Strong hands-on experience in:
  • Scan Insertion
  • ATPG
  • MBIST
  • JTAG / Boundary Scan
  • DFT Verification
  • Scan Compression
  • Knowledge of ASIC/SOC design flow.
  • Experience with synthesis and STA concepts.
  • Good understanding of digital design fundamentals.

Preferred EDA Tools

  • Synopsys DFT Compiler
  • Tessent Scan / MBIST
  • TetraMAX / TestMAX ATPG
  • SpyGlass DFT
  • Modus (Cadence)

Desired Candidate Profile

  • Bachelor's/Master's Degree in Electronics/ECE/VLSI.
  • Experience in ASIC/SOC development projects.
  • Good debugging and problem-solving skills.
  • Excellent communication and stakeholder management skills.

More Info

Job Type:
Industry:
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Key Skills

ASIC SOC design flow

digital design fundamentals

JTAG Boundary Scan

Scan Compression

STA concepts

DFT Verification

About Company

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