Senior DFT Engineer
Quess Corp- Posted 2 hours ago
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Job Description
We are Hiring | Lead/Senior DFT Engineer (3024) | Semiconductor MNC | 9–12 Years
We are looking for experienced DFT professionals for an exciting opportunity with a leading Semiconductor MNC!
Experience: 9–12 Years
Role: Senior / Lead DFT Engineer
Domain: Semiconductor / VLSI / ASIC
Interview Mode: Virtual / In-person
Mandatory Skills
DFT – Scan/ATPG
- Strong hands-on experience in Scan/ATPG, DRC, and coverage analysis.
- Expertise in Tessent tools, SSN/EDT, and scan pattern generation.
- Experience with Stuck-at, Transition, Cell-Aware, and AFM fault models.
- Hands-on experience in scan pattern simulation, debugging, and coverage analysis.
DFX Design Verification
- Experience in DFX DV for IP, debug units, clock/analog observe, PLL, RO, and thermal sensors.
- Knowledge of JTAG networks, Boundary Scan, TDR verification, and clock-stop features.
- Strong verification fundamentals, test-case development, coverage analysis, debugging, and root-cause analysis.
Important: Candidates must have strong expertise in at least one of the two areas: DFT Scan/ATPG or DFX Design Verification. Scan/ATPG expertise is preferred.
Good to Have
- Experience with AMD flows and methodologies.
- Scripting skills and strong analytical and problem-solving abilities.
- Ability to work independently, take ownership, and collaborate effectively with teams.
Interested candidates can share their updated resumes via DM.
#Hiring #DFT #ScanATPG #SemiconductorJobs #VLSI #ASIC #Tessent #DFX #DesignVerification #SeniorEngineer #LeadEngineer #EngineeringJobs
More Info
Key Skills
Tessent tools
clock analog observe PLL RO
DFT – Scan ATPG
thermal sensors
SSN EDT
JTAG networks
DFX DV for IP debug units
TDR verification
clock-stop features
scan pattern generation
test-case development
AFM fault models
scan pattern simulation
root-cause analysis
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