DFT Engineer
- Posted a month ago
- Be among the first 10 applicants
Job Description
DFT Engineer
Location: Bangalor
eNotice Period: Immediate to 30 days
Job Description:We are looking for a skilled DFT Engineer with 4–8 years of experience in ASIC design and verification with a strong focus on Design-for-Test methodologies. You will be responsible for implementing and verifying DFT architectures to ensure high test coverage and manufacturability.
Key Responsibilities:
- Develop and implement DFT architecture including scan insertion, ATPG, MBIST, and boundary scan.
- Work on RTL design modifications for DFT features
- Generate and validate test vectors using tools like Tetramax/Fastscan
- Run gate-level simulations and debug test coverage issues
- Perform pattern validation on emulation/silicon platforms
- Collaborate with RTL, PD, and validation teams for seamless DFT integration.
Required Skills:
- Strong knowledge of DFT concepts: scan, compression, boundary scan, ATPG, BIST (LBIST/MBIST).
- Experience with tools such as Synopsys DFT Compiler, Tetramax, Mentor Tessent.
- Scripting skills in Python, Perl, or TCL for automation.
- Familiarity with STA, synthesis, and timing constraints
- Good understanding of RTL-to-GDS flow
Good to Have
- Exposure to automotive or high-reliability designs
- Experience with silicon bring-up and pattern debug.
More Info
Job Type:
Industry:
Function:
Employment Type:
Key Skills
scan compression
DFT concepts
STA synthesis
Synopsys DFT Compiler
LBIST
RTL-to-GDS flow
Mentor Tessent
About Company
Skills:
Jtag, Perl, Python, NVIDIA custom tools, Memory BIST, SV, ATPG, Uvm
Skills:
Scripting skills: Tcl, boundary scan , Vcs, System Verilog, Memory BIST, primetime, Logic Equivalency checking, Post-silicon validation and debug, P1687, TetraMax, Gate level simulation debugging, ATE patterns, JTAG protocols, ATPG, EDA Tools, BIST architectures, Tessent tool sets, TestMax
Skills:
Logic Built-In Self-Test (LBIST), Automatic Test Pattern Generation (ATPG), ATPG tools (Mentor TK), Static timing analysis, Timing Closure, Debug skills, On-chip test compression techniques, Scripting skills, Structural DFT, DFT Architecture and Design
Skills:
Jtag, Dft, ATPG, Scan Insertion
Early Applicant
Skills:
Shell Scripting, Perl, Python, Tcl, Design Compiler, Verdi, ATPG Pattern Generation, RTL Netlist, primetime, JTAG Boundary Scan, Tessent Scan, Fault Coverage Analysis, Synopsys DFTMAX, Tessent ATPG, Tessent MBIST, Test Collateral, Siemens Tessent Tool Suite, Tessent Diagnosis, Scan Insertion, Scan Compression, MBIST Architecture Implementation