Jtag, Perl, Python, NVIDIA custom tools, Memory BIST, SV, ATPG, Uvm

Scripting skills: Tcl, boundary scan , Vcs, System Verilog, Memory BIST, primetime, Logic Equivalency checking, Post-silicon validation and debug, P1687, TetraMax, Gate level simulation debugging, ATE patterns, JTAG protocols, ATPG, EDA Tools, BIST architectures, Tessent tool sets, TestMax

Logic Built-In Self-Test (LBIST), Automatic Test Pattern Generation (ATPG), ATPG tools (Mentor TK), Static timing analysis, Timing Closure, Debug skills, On-chip test compression techniques, Scripting skills, Structural DFT, DFT Architecture and Design

Jtag, Dft, ATPG, Scan Insertion

Shell Scripting, Perl, Python, Tcl, Design Compiler, Verdi, ATPG Pattern Generation, RTL Netlist, primetime, JTAG Boundary Scan, Tessent Scan, Fault Coverage Analysis, Synopsys DFTMAX, Tessent ATPG, Tessent MBIST, Test Collateral, Siemens Tessent Tool Suite, Tessent Diagnosis, Scan Insertion, Scan Compression, MBIST Architecture Implementation

MBIST Insertion Verification, ATPG Coverage Analysis Debug, Scan Insertion Compression, Boundary Scan Verification, Mentor Cadence Synopsys Tools

boundary scan , Perl, Tcl, test compression, scan compression, DFT signoff, pattern optimization, test access strategies, MBIST, DFT architecture definition, ATPG, yield ramp, LBIST, first silicon bring-up