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Hello Connections
Greetings from Tessolve Semiconductors!!
Design and Verification Engineer
Verification Engineer/Sr. Engineer/Lead/Managers – ASIC/IP/SOC/CPU (Design Verification )
Location : India/Abroad
Experience - 7+
• IP verification Using SV/UVM
• SOC Verification using C/SV
• Third Party VIP Integration
• Interconnect Protocols: AHB, AXI, APB
• SOC Interfaces: GPIO, SPI, I2C, UART (5+)
• High Speed Serial Interfaces: PCIe Gen 3/4 or USB or MIPI (7+)
• Memory Interfaces: DDR or HBM I/O (10+)
• Coverage Closure: Code, Functional and Toggle
• Tools: Synopsys VCS or Cadence Incsive
• Technical Documentation: Testbench Specification, Test Plan Specification
• Foundry Porting Experience: Technology Library Conversion Related Changes Verification
Please share your CV to [Confidential Information]
Job ID: 144755647
Skills:
SOC Interfaces, SV/UVM, C/SV
Skills:
test environments , C, Soc Architecture, Test Cases, Shell, Verilog, Python, industry-standard simulators, Mixed signal designs, SV, regression systems, Uvm, revision control systems, verification testbenches
Skills:
Pcie, Nvme, DDR, UVM-based SV test-benches, CPU sub-systems, quality metrics, verification methodologies, NAND
Skills:
Perl, Verilog, Python, Tcl, Synopsys VCS, SystemVerilog Assertions, Mentor Questa, Cadence Xcelium, VHDL, Uvm, systemverilog
Skills:
code coverage , Ethernet, Pcie, Uvm, SV, formal-based verification, mixed signal IP, PIPE, Specman, AMBA, DDR verification, SERDES
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