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ACL Digital Hiring for the below requirement
Designation: DV engineers
Experience: 4 -10+ years
Location: Bangalore / Hyderabad
Job Description:
1. Hands-on experiences on SV/UVM/Specman
2. Familiarity with formal-based verification
3. Running regression and debugging failures independently
4. Experience in functional and code coverages
5. Independently handling sub-module-level verification
6. Clear written/verbal communication skills.
7. Familiarity with PIPE i/f or Ethernet is a must; it's good to have basic knowledge of PCIe and AMBA.
8. Familiarity in mixed signal IP (SerDes, DDR) verification will be a plus.
Job ID: 144789379
Skills:
bandwidth management , Microprocessor Cores, Specman E, hierarchical memory subsystems, Debug, interconnects, IP subsystem SoCs, congestion control, systemverilog, constrained-random verification, packet processing, Verification, standard IP components
Skills:
scoreboard , System Verilog, verification environment, verification closure, script development, interface agents, Uvm, testbench components
Skills:
Fpga, hardware emulation, simulation platforms, IEEE 1500, verification methodologies, IEEE 1149.1, Palladium, Uvm, systemverilog
Skills:
Usb, Fpga, Pcie, Perl, Python, verification methodologies, Emulation, coverage driven verification, directed constrained-random tests, Uvm, systemverilog, AMBA, formal verification, MIPI, Test Bench, transaction level modeling, AXI4
Skills:
Vcs, Git, Pcie, Ethernet, System Verilog, low-power verification techniques, cdc, Uvm, UPF, C Language, Axi, level shifter implementation, AMBA, FIFOs, APB, Questa, RISC-V CPU subsystems, clock reset architectures, power management strategies, AHB
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