SOC Interfaces, SV/UVM, C/SV

test environments , C, Soc Architecture, Test Cases, Shell, Verilog, Python, industry-standard simulators, Mixed signal designs, SV, regression systems, Uvm, revision control systems, verification testbenches

Pcie, Nvme, DDR, UVM-based SV test-benches, CPU sub-systems, quality metrics, verification methodologies, NAND

Perl, Verilog, Python, Tcl, Synopsys VCS, SystemVerilog Assertions, Mentor Questa, Cadence Xcelium, VHDL, Uvm, systemverilog

code coverage , Ethernet, Pcie, Uvm, SV, formal-based verification, mixed signal IP, PIPE, Specman, AMBA, DDR verification, SERDES

Soc Architecture, Shell, Perl, System Verilog, Python, Cadence Xcelium, Simulation Tools, Uvm, Synopsys VCS, digital design concepts, Axi, AMBA, APB, AHB, debugging using waveforms and logs

simvision , Cmake, Shell, Perl, Python, Verdi, Cadence Xcelium, JasperGold, Palladium, make, Uvm, UPF, systemverilog, Siemens Questa, Synopsys VCS, Zebu, DVE, Veloce, PropCheck, CPF, VC Formal, SVA

bandgap references , mixed signal design architectures, verification debug, Uvm, SV, power management, DACs, analog mixed signal behavioral modeling, ADCs, full chip verification, self-checking testcases, Oscillators, verification environment development, SERDES, Pll