Senior SOC Design Verification Engineer

Company Description Chiplogic Technologies is an IP and product engineering services company founded in 2018, specializing in semiconductor, systems, IoT, and AI/ML solutions. The organization delivers high-quality, dependable services across the full semiconductor lifecycle, from concept to silicon. Chiplogic provides ODC and full turnkey design and system solutions, including proof-of-concept development and final IoT system implementations. The company also offers AI/ML services built around its proprietary VISARD™ (Video Synthesis And Real-time Dynamics) framework, enabling advanced video and real-time analytics applications. Team members work on cutting-edge technologies and end-to-end product development in a collaborative environment.

Role Description About the Role

We are looking for an experienced Senior SoC Design Verification Engineer with 5+ years of hands-on experience in ASIC/SoC Design Verification. The ideal candidate should have strong expertise in SystemVerilog, UVM, C programming, and SoC-level verification, along with experience in developing verification environments, test plans, debugging, and functional coverage closure.

Key Responsibilities

• Develop and execute comprehensive verification plans and test strategies for complex SoC designs.
• Build and maintain UVM-based verification environments using SystemVerilog.
• Perform SoC-level functional verification, including subsystem integration and system-level validation.
• Develop test cases, sequences, and testbench components to verify complex design functionality.
• Perform RTL simulation, debugging, regression analysis, and functional coverage closure.
• Work on C-based test development and firmware-driven verification.
• Verify SoC interfaces, bus protocols, memory subsystems, interrupts, resets, clocking, and power management features.
• Collaborate with RTL designers, architects, firmware, and validation teams to resolve design issues.
• Identify functional gaps, debug failures, and drive verification sign-off.

Mandatory Technical Skills

• 5+ years of hands-on experience in ASIC/SoC Design Verification.
• Strong proficiency in SystemVerilog and UVM.
• Solid experience in SoC-level verification rather than exclusively IP-level verification.
• Good programming skills in C/C++.
• Strong understanding of digital design concepts and RTL verification methodologies.
• Experience in developing UVM testbenches, sequences, monitors, drivers, and scoreboards.
• Hands-on experience with simulation and debugging tools such as VCS, Questa, or Xcelium.
• Knowledge of functional coverage, code coverage, assertions, and regression methodologies.
• Good understanding of on-chip bus protocols such as AMBA AXI, AHB, or APB.

Good to Have

• Experience in firmware-driven and C-based SoC verification.
• Knowledge of PCIe, USB, Ethernet, DDR, or other high-speed interfaces.
• Exposure to formal verification and SystemVerilog Assertions (SVA).
• Experience with power management, reset, clock-domain crossing (CDC), and low-power verification.
• Familiarity with scripting languages such as Python, Perl, or Shell.

Candidate Profile

• Strong debugging and analytical skills.
• Ability to independently own verification activities.
• Good communication and collaboration skills.
• Experience working in cross-functional ASIC/SoC development teams.

Interested candidates can share their updated resumes with:

Email: [Confidential Information]

• Immediate joiners are highly preferred.