C, C++, Vcs, Debugging, RTL simulation, on-chip bus protocols, Xcelium, Uvm, systemverilog, SoC-level verification, AMBA, Axi, APB, Questa, AHB, functional coverage

bandwidth management , Machine Learning, Artificial Intelligence, SystemVerilog Assertions, Specman E, Debug, formal tools, IP subsystem SoCs, congestion control, AI ML accelerators, systemverilog, memory system architecture, vector processing units, ASIC standard interfaces, packet processing, Verification, Universal Verification Methodology

Usb, Mac, Pcie, Perl, Ethernet, Shell scripting, System Verilog, Python, Tcl, AHB-Lite, Uvm, AMBA, Axi, APB

Fpga, Usb, Perl, Pcie, Python, verification methodologies, Emulation, coverage driven verification, directed constrained-random tests, Uvm, systemverilog, AMBA, MIPI, formal verification, Test Bench, transaction level modeling, AXI4

Tcl Scripting, Unix Shell Scripting, Perl, Verilog, System Verilog, Debugging, Incisive, IMC, analog mixed signal design, Uvm, advanced verification methodologies, xCelium, vManager, Cadence Virtuoso, test bench development, verification IP, object-oriented programming, Simulation, behavioral modelling, mixed signal verification environment, verification plans, analog blocks

Shell, Perl, Verilog, Python, Tcl, Functional and code coverage, Simulation and debugging concepts, Automation scripts, Assertions SVA, UVM methodology, systemverilog

Pcie, Perl, Vcs, Ethernet, Python, Tcl, Verdi, Uvm, systemverilog

Ovm, Debugging, Test Planning, CHI, SoC design verification, AMBA protocols, Uvm, UVM-based test benches, system simulation tools, Axi, APB, emulation models, AHB