

Search by job, company or skills

Silicon Verification Engineer
We have open positions at the Senior, Staff, and Principal levels. Your application will be evaluated based on your overall experience and alignment with the requirements of the respective level.
Please note: If you have already interviewed for the same role within the last 6 months, please refrain from applying again.
Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption.
As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world's most transformative technologies. We are opening a new AI Engineering Campus in Bengaluru, which will play a central role in Graphcore's work building the future of AI computing.
The verification team sits within the Silicon design team and is responsible for ensuring that the RTL created by the logical design team and used by the physical design team matches the architecture specification for Graphcore silicon. The silicon verification engineer is responsible for verification activities within Graphcore, helping the team meet the company objectives for quality silicon delivery.
Responsibilities
Essential Skills
Desirable Skills
Benefits
In addition to a competitive salary, Graphcore offers a competitive benefits package. We welcome people of different backgrounds and experiences; we're committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to the interview and encourage you to chat to us if you require any reasonable adjustments.
Job ID: 153874973
Skills:
Usb, Vcs, DDR, Pcie, Ethernet, System Verilog, Xcelium, UVM methodology, UCIE, Axi, Questa, CXL
Skills:
Verilog, System Verilog, Assertion Checker Development, Coverage Closure, Functional Coverage Development, Testcase Planning Development, UVM Testbench Coding, Design Verification Failure Debugging, Concepts in Digital Design
Skills:
Pcie, Perl, Python, Tcl, protocol-level debugging, simulation and debug tools, verification methodology, UCIe, Uvm, FDI, systemverilog, coverage closure, CXL, RDI, SVA
Skills:
Perl, Verilog, Python, Uvm, SVA, systemverilog
Skills:
Shell, Perl, Verilog, Python, Tcl, LINT, Makefiles, Cadence Xcelium, JasperGold Formal, Cadence VCS, QuestaSim, Uvm, systemverilog, Questa Formal, VHDL, Modelsim