Usb, Vcs, DDR, Pcie, Ethernet, System Verilog, Xcelium, UVM methodology, UCIE, Axi, Questa, CXL

Verilog, System Verilog, Assertion Checker Development, Coverage Closure, Functional Coverage Development, Testcase Planning Development, UVM Testbench Coding, Design Verification Failure Debugging, Concepts in Digital Design

Pcie, Perl, Python, Tcl, protocol-level debugging, simulation and debug tools, verification methodology, UCIe, Uvm, FDI, systemverilog, coverage closure, CXL, RDI, SVA

Perl, Verilog, Python, Uvm, SVA, systemverilog

Shell, Perl, Verilog, Python, Tcl, LINT, Makefiles, Cadence Xcelium, JasperGold Formal, Cadence VCS, QuestaSim, Uvm, systemverilog, Questa Formal, VHDL, Modelsim

Perl, Ovm, Python, Axi, APB, AMBA protocols, Uvm, AHB, systemverilog

static timing analysis, Digital Logic Design, Perl, Verilog, Python, Scripting, Tcl, Synthesis, cdc, memory subsystems, SOC design, Uvm, IP integration, systemverilog, Rtl Design, Axi, formal verification, EDA tool flows, LINT, Verification, Microarchitecture, bus architectures, automation of design flows

Usb, Vcs, DDR, Pcie, Perl, Ethernet, Shell scripting, Python, Tcl, Xcelium, Uvm, systemverilog, Questa

DDR, Usb, Pcie, Ethernet, SV, CXL, Uvm