Sr. Design Verification Engineer
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5+ Years Experience in System Verilog and UVM methodology
Hands-on expertise in high-speed interface protocols (PCIe / CXL/UCIE/USB / DDR / Ethernet / AXI, etc.)
Good understanding of verification concepts, coverage, assertions, and debugging
Experience with simulation tools (VCS, Questa, Xcelium, etc.)
Strong analytical & problem-solving skills
Job ID: 153867975
Skills:
Tcl, System Verilog, Python, Pcie, Perl, SVA, assertion-based verification, Coresight, Uvm, UPF, SMMU, CHI, coverage-driven testing, CXL, formal verification, power-aware verification, Axi
Skills:
code coverage , System Verilog, IC verification tools, Cover groups, DIMM, DDR5, DDR4, Uvm, Functional coverage, Assertions, LPDDR5
