Design Verification Engineer
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Design Verification Engineer - Senior / Lead / Sr. Lead
Job Description:
having SOC/IP performance verification background is added plus
Experience: 4 to 12 Years
Location: Bangalore / Hyderabad
Work Mode: Work from Office (WFO)
Job ID: 153636797
Skills:
Git, Mercurial, Svn, GLS Simulations, low power design, Uvm
Skills:
Usb, Mac, Perl, Pcie, Ethernet, Shell scripting, System Verilog, Python, Tcl, AHB-Lite, Uvm, AMBA, Axi, APB
Skills:
Usb, Can, Lin, Flexray, Pcie, Verilog, Ethernet, System Verilog, Functional Coverage Development, UVM Testbench Coding, IP SOC Verification, Design Verification Failure Debugging, Axi, Coverage Closure, APB, Assertion Checker Development, Testcase Planning Development, CXL, AHB, Digital Design
Skills:
Fpga, Logic Design, Verilog, Sta, Synthesis, Power product design, TCL scripts, Scan Insertion, Timing Analysis, design constraints, Uvm, ATPG generation, regression frameworks, formal verification, Timing Constraints, synthesis scripts, ABV, RTL Coding, micro-architecture, Functional Verification, System-Verilog, Digital Verification
Skills:
Jtag, C, Verilog, System Verilog, Uvm
