Git, Mercurial, Svn, GLS Simulations, low power design, Uvm

Usb, Mac, Perl, Pcie, Ethernet, Shell scripting, System Verilog, Python, Tcl, AHB-Lite, Uvm, AMBA, Axi, APB

Usb, Can, Lin, Flexray, Pcie, Verilog, Ethernet, System Verilog, Functional Coverage Development, UVM Testbench Coding, IP SOC Verification, Design Verification Failure Debugging, Axi, Coverage Closure, APB, Assertion Checker Development, Testcase Planning Development, CXL, AHB, Digital Design

Fpga, Logic Design, Verilog, Sta, Synthesis, Power product design, TCL scripts, Scan Insertion, Timing Analysis, design constraints, Uvm, ATPG generation, regression frameworks, formal verification, Timing Constraints, synthesis scripts, ABV, RTL Coding, micro-architecture, Functional Verification, System-Verilog, Digital Verification

Jtag, C, Verilog, System Verilog, Uvm