L
Design Engineer
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Design Engineer
L&T Technology Services- Posted an hour ago
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Job Description
We are seeking an experienced RTL Design Lead to drive the architecture, design, and delivery of complex ASIC/SoC projects. The ideal candidate will possess strong RTL design expertise, technical leadership skills.
Experience : 7 to 16 Yrs
Location : Bangalore
Key Responsibilities
- Lead end-to-end RTL design development for complex ASIC/SoC programs.
- Define micro-architecture and guide the implementation of high-quality RTL designs.
- Lead IP/subsystem integration and ensure adherence to design methodologies.
- Review RTL code, architecture documents, and design specifications.
- Mentor and technically guide a team of RTL engineers.
- Drive design reviews, technical discussions, and issue resolution.
- Collaborate with DV, DFT, Physical Design, STA, and Firmware teams for successful project execution.
- Ensure design quality through Lint, CDC, RDC, and synthesis checks.
- Support project planning, resource allocation, effort estimation, and risk management.
- Interface with customers and stakeholders on technical deliverables and project status.
Required Skills
- Strong expertise in RTL Design using Verilog/SystemVerilog.
- Proven experience in ASIC/SoC Design and Architecture.
- Hands-on experience in:
- Micro-Architecture Development
- RTL Coding and Integration
- Lint, CDC, RDC
- Synthesis and Timing Analysis
- Design Debug and Root Cause Analysis
- Strong understanding of AMBA protocols:
- AXI
- AHB
- APB
- Experience with high-speed interfaces such as PCIe, DDR, Ethernet, USB, or SerDes.
- Excellent technical leadership and stakeholder management skills.
More Info
Key Skills
AMBA protocols
Micro-Architecture Development
RDC
RTL Coding and Integration
Design Debug
About Company
Skills:
C, Clearcase, Cryptography, Aes, Encryption, Clearquest, Perl, Verilog, Python, System Verilog, LINT, cdc, RTL design using Verilog, hash functions, GMAC, signatures, LEC, SHA, private key, ASIC development tools, random number generator
Skills:
Routing, CTS, Power performance and area PPA optimization, Fusion Compiler, floorplanning, LVS, EM analysis, Optimization, Physical Verification, RTL-to-GDSII implementation, EDA Tools, Timing Closure, Placement, DRC, Physical design flow, Congestion analysis, Synopsys ICC2, Signal Integrity, Timing Analysis
Skills:
micro architecture , X86, Computer Architecture, Arm, Prefetch Coherency, ECO bring up, Design Verification, Fetch Decode Load-Store, high performance microprocessor architecture, Processor ASIC design flow, L1 L2 caches, Memory Design, CPU microarchitecture, Processor Instruction set architecture, PD synthesis, Rtl Design, Memory Ordering Rules, PPA optimization, Power
Skills:
Perl, Shell scripting, Python, Sta, SDC constraints, RTL design using Verilog, ASIC SoC development, Timing Analysis, systemverilog, digital design concepts, VHDL, Functional Verification, RTL debugging, UVM-based verification environments, Timing Closure, synthesis flows
Skills:
PCIe Gen 1 2 3, EMI mitigation techniques, DDR3 DDR4 LPDDR4 routing, Altium Designer, Power distribution networks, MIPI-CSI DSI, USB 3.x, HDMI, High-speed multi-layer PCB design, Controlled impedance design, gigabit ethernet