C, Clearcase, Cryptography, Aes, Encryption, Clearquest, Perl, Verilog, Python, System Verilog, LINT, cdc, RTL design using Verilog, hash functions, GMAC, signatures, LEC, SHA, private key, ASIC development tools, random number generator

Routing, CTS, Power performance and area PPA optimization, Fusion Compiler, floorplanning, LVS, EM analysis, Optimization, Physical Verification, RTL-to-GDSII implementation, EDA Tools, Timing Closure, Placement, DRC, Physical design flow, Congestion analysis, Synopsys ICC2, Signal Integrity, Timing Analysis

micro architecture , X86, Computer Architecture, Arm, Prefetch Coherency, ECO bring up, Design Verification, Fetch Decode Load-Store, high performance microprocessor architecture, Processor ASIC design flow, L1 L2 caches, Memory Design, CPU microarchitecture, Processor Instruction set architecture, PD synthesis, Rtl Design, Memory Ordering Rules, PPA optimization, Power

Perl, Shell scripting, Python, Sta, SDC constraints, RTL design using Verilog, ASIC SoC development, Timing Analysis, systemverilog, digital design concepts, VHDL, Functional Verification, RTL debugging, UVM-based verification environments, Timing Closure, synthesis flows

PCIe Gen 1 2 3, EMI mitigation techniques, DDR3 DDR4 LPDDR4 routing, Altium Designer, Power distribution networks, MIPI-CSI DSI, USB 3.x, HDMI, High-speed multi-layer PCB design, Controlled impedance design, gigabit ethernet

simulation and verification flow, DFT design and verification, silicon bringup, DFT technologies, fault modeling, ASIC DFT synthesis, IP integration, DFT specification definition, silicon debug activities

Design for Manufacturability, Physical Design, Timing Closure Methodologies, Placement and Routing, Design Rule Checks, Clock Tree Synthesis

Computer Architecture, C, Perl, Verilog, Python, System Verilog, Vlsi, CAD, Chip Floorplan, Power Distribution, Timing Closure, Physical Design Methodologies