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ASIC RTL Design

L&T Technology Services
Bengaluru, India
5-7 Years
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  • Posted 2 days ago
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Job Description

Below is the JD for RTL engg. We need to build strong RTL team.

  • Minimum 5 years of work experience in ASIC RTL Design, Synthesis, STA & FV
  • Experience in Logic design/micro-architecture/RTL coding is a must.
  • Must have hands on experience with design and integration of complex multi clock domain blocks
  • Experience in Verilog/System-Verilog is a must.
  • Should have knowledge of AMBA protocols - AXI, AHB, APB, clocking/reset/debug architecture
  • Hands on experience in Multi Clock designs, Asynchronous interface is a must.
  • Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required.
  • Work closely with the Design verification and validation teams for pre/post Silicon debug
  • Hands on experience in Low power design is preferable
  • Experience in Synthesis / Understanding of timing concepts for ASIC is must

More Info

Job Type:
Permanent Job
Industry:
Other
Function:
Asic Rtl Design
Employment Type:
Full time

Job ID: 148271575

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Last Updated: 24-05-2026 05:09:45 PM
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